As technology continues to infiltrate everyday life, users are demanding increased speed and reliability of computerized equipment. In order to satisfy the demand for increased speed, increasingly powerful and complex processors are being designed and manufactured. However, as the complexity of these processors increases, it becomes more difficult to verify their correct behavior. If a processor fails to function as intended, due to an error, the results could be catastrophic to a user.
In order to verify the behavior of a processor that is still in the developmental stage, developers often use a testcase generator. A testcase generator automatically generates a large number of testcases that it then performs on a processor to test its functionality. A testcase is a text file that contains resource state initialization information and test instructions to be run on a simulator of a processor under development. When a testcase is run, the simulator's resources are initialized to the state specified in the testcase and the instructions specified are executed on the processor simulator being tested. Testcase instructions may include, but are in no way limited to, add, load, and store operations.
Typically, testcase generators randomly select parameters for each testcase in order to create a large number of testcases that cover a wide variety of instructions and test the various functionality of the processor under development. These testcases are run to exercise a processor's control paths more fully than typical program code, which for performance reasons, often deliberately avoids performing operations that it is known are difficult for a processor to perform.
Some testcase generators are able to further evaluate a processor under development by generating what are commonly known as “predictable” testcases. Predictable testcases occur when a testcase generator is able to predict the sequence of instructions and data that a processor will use while performing a testcase. When performing predictable testcases, the testcase generator predicts the final state of the processor resources. The predicted final state of the processor resources is then compared to the actual final state of the simulated processor under development to determine whether the correct results were achieved. If the predicted and the actual final states of the simulated processor under development differ, an error has occurred and the processor should be debugged either manually or automatically.
Many processors also have the capability to simultaneously run multiple “threads” of code. When multiple threads of code are simultaneously being performed, a condition known as data sharing may occur. Data sharing occurs when two or more separate threads operate on the same “line” of data. A “line” of data is the smallest set of data that may be loaded into cache in a particular processor. For example, a processor may have a data line size of 32-bytes. If a thread uses any byte of data on a particular 32-byte line, the entire 32-byte line will be loaded into cache of the processor. If an additional thread of code operates on the same line of data, both threads may access the cached data resulting in a data sharing situation.